1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a planarization process for a pre-damascene structure that includes a metal hard mask.
2. Description of the Related Art
Damascene techniques are frequently used to form interconnect structures. In a conventional damascene process, a dielectric layer is formed and then patterned using a hard mask to form a damascene opening therein, a metal layer is formed filling the damascene opening, the metal layer outside the opening is removed through chemical mechanical polishing (CMP), and then the hard mask is removed. In the related art, the process of removing the metal layer outside the damascene opening through CMP is considered as a planarization process.
However, as the linewidth of semiconductor devices becomes smaller, the conventional SiO or SiN hard mask is no longer satisfactory for the requirements in critical dimension (CD). Therefore, metal hard masks are reported to use in advanced semiconductor processes. In the prior art, a metal hard mask is removed through dry- or wet-etching after the metal layer filling the damascene opening is planarized through CMP.